DRC, LVS and PEX using Calibre-2014.3 with Cadence IC615

In this tutorial I will use the IBM 7RF(180nm CMOS) process as the reference. I will talk about the basic settings for using the Calibre DRC, LVS and PEX. Most importantly, I will comment on some issues I met.

I talked in details about build up one basic inverter schematic using the Schematic tool, created a symbol and a layout using the Virtuoso Layout editor. I will verify the inverter layout meets the process specific design rules using the Calibre DRC, then make sure that the schematic and layout match by using the Calibre LVS.  In final, I extracted an equivalent circuit with associated layout parasitics using Calibre PEX. The extracted cellview was imulated by using Analog Design Environment and Spectre.

1. Getting Started

First, we need to edit the bashrc for using Calibre tool in you home directory. I paste the script as bellow. The calibre software directory should be exported and also for the PATH. When I launched calibre at first, I met a issue related to IXL: “Error: Current execution environment is VCO=aoi. Software tree is for environment VCO=ixl”. So in bashrc file, I add CALIBRE_2013_4_ALLOW_IXL_ON_RHEL6=101010 to kill the error.

######CALIBRE – DRC, LVS, parasitic extraction ###########
export MGC_HOME=/xxxxx/xxx/xxxx/calibre/ixl_cal_2014.3_27.21
export CALIBRE_HOME=$MGC_HOME
export PATH=$MGC_HOME/bin:$PATH
export CALIBRE_2013_4_ALLOW_IXL_ON_RHEL6=101010

2. Add IBM7RF Process Kit

For using the IBM7RF PDK, I installed the process kit into IBM7RF folder so that the subfolder IBM_PDK contained everything for IBM7RF process kit.

Then I copied .cdsinit, .cdsenv,cds.lib and display.drf from the directory: /home/xxx/IBM7RF/IBM_PDK/cmrf7sf/V2.0.1.0AM/cdslib/examples into IBM7RF paralleling IBM_PDK.

And I also need to edit the cds.lib for libraries directory definition.

DEFINE cmrf7sf /home/xxxx/IBM7RF/IBM_PDK/cmrf7sf/V2.0.1.0AM/cdslib/cmrf7sf
DEFINE esd7rf /home/xxxx/IBM7RF/IBM_PDK/cmrf7sf/V2.0.1.0AM/cdslib/esd7rf
DEFINE analogLib $AMIS_DFII_DIR/tools.lnx86/dfII/etc/cdslib/artist/analogLib
DEFINE sbaLib $AMIS_DFII_DIR/tools.lnx86/dfII/etc/cdslib/artist/sbaLib
DEFINE basic $AMIS_DFII_DIR/tools.lnx86/dfII/etc/cdslib/basic
DEFINE sheets $AMIS_DFII_DIR/tools.lnx86/dfII/etc/cdslib/sheets/US_8ths
DEFINE sample $AMIS_DFII_DIR/tools/dfII/samples/cdslib/sample

Finally, I created a folder my7RFdesign to contain my design using IBM 180nm process. In this work directory, we have to cp cds.lib, .cdsinit, .cdsenv,display.drf from IBM7RF.

(BTW: I get used to the keybinding of Cadence so I commented all the Bindkey settings in .cdsinit for IBM process. )

Now under my7RFdesign, open a terminal and launch IC615 by typing virtuoso&. The Cadence CIW window will pop up. The IBM_PDK will be shown in the CIW menu.

Click Tools—>Library Manager and several libraries defined in cds.lib will be shown here. And they are black not gray. If you see your libraries are gray, it means that the cds.lib editing is not successful.

3. Create a New Library

To create a new library, select IBM_PDK > Library > Create, the ‘New Library’ window will open.

Name the new library and select the button ‘Compile an ASCII technology file’. Then the ASCII file browser window will open and click the Browser button. Go to /home/xxxx/IBM7RF/IBM_PDK/cmrf7sf/V2.0.1.0AM/cdslib/cmrf7sf and select the file type as ‘*’ instead of ‘.tf’. You will see several ’techfile*.asc‘ in this folder. Different technology file is setup for how many metals you are going to use in the design. I select techfile7.asc and click OK. The message window tells you that the technology file are loading successfully. At the same time, the ‘Add IBM PDK library properties’ window will be shown and it tells you how many number of levels of metal you are going to use and the supply spec. Click OK and the new library will be in the Library manager.

4. Create a inverter schematic

Open the ‘library manager’ (Tools > Library Manager) and select the library you created. Now create the new schematic cellview (File > New > Cell View).

In the ‘New File’ window, please name the cell and select the ‘schematic’ Type. Sometimes, you have to select the Application by open with Schematic L or Schematic XL because of Cadence License issues. If you didn’t do that, you will see an warning message in CIW, it tells you that ‘Schematic L license is not available to run and check out the licence Virtuoso_Schematic_Editor_XL instead (95515). (it means that Cadence automatically used a Schematic XL license to open the schematic cell instead of Schematic L)’. But actually, it doesn’t affect the design.

After schematic window open, type ‘I’ to insert the components. Click ‘cmrf7sf’ and select nfet or pfet (NMOS or PMOS). Close the library browser window and edit the width/length in the property window of nfet/pfet. For this tutorial, I used 2u/180n for PMOS and 1u/180n for NMOS. The bulk node of nfet/pfet isn’t shown in schematic. But we can see the detail of bulk in the property window. For nfet, B is connected to sub! (substrate) and for pfet, B is connected to vdd!.
(BTW: you can use other models for test like nfet25, nfet25_rf, nfet25tw_rf, … etc. But before using them, you have to look up the manual to understand what is their difference. )

Complete the inverter schematic following the model figure I created. There has a substrate model ‘subc’ which has one node connected to gnd!. The inverter cell has one input and output. The ground is connected to gnd! and supply is connected to vdd!. Right here, these steps you have to know how to create label and pins.

5. Create a Symbolic View

In the schematic window, click Create > Cellview > From Cellview. This will open ‘Cellview from Cellview’ menu. The library name and cellview name should be the same used in your schematic. ‘From View Name’ should be schematic. ‘To View Name’ should be symbol. Select OK.

You should have two pin names, ‘in’ as a left pin and ‘out’ as a right pin. The global net names vdd! and gnd! have been used for supplies so they will not show up as pins in this instance. With the symbol generation options complete, select OK.

The appearance of the symbol will be shown up. Make sure you can edit your symbol like this figure. Finally, save your symbol and close it.

6. Create a Layout

Select the schematic cell and then click File > New > CellView. In the new file window, select the Type as Layout and Open with Layout XL or Layout GXL. Then Virtuoso will automatically open Schematic and Layout two windows. You can click connectivity > Generate > All From Source. Those layout component will be located in Layout cell. Follow the figure to connect the layout components.

The ‘nwCont’ is to connected NWell to vdd!; the ‘subc’ is to connected substrate to gnd! and there are a resistor between substrate and ground. Pay attention to three layers: sub is for substrate layer; SXCUT label is to label the substrate as sub!; the ‘GRLOGIC’ is used to cancel one DRC error.

7. DRC & LVS

Some tutorials told us to select Calibre > Run nmDRC… But for IBM7RF PDK, if you did that, you will get an error to setup the DRC. So every time we want to run DRC or LVS we have to select IBM_PDK on the Layout top menu > Checking > Calibre > DRC/LVS. Then the cmrf7sf Environmental Variable Setup window will be shown up. (window1,window2)

For the detail setup, I will talk later. For this tutorial, I focus on making the DRC working. So I setup BEOL_STACK>7; DESIGN_TYPE>CELL;PEX_RULES>cmrf7sf_7AM.xrc.cal.

After clicking OK, the DRC window will open and the DRC rules files has been already loaded. You can set the DRC Run Directory to anything. I created a new folder so that all the DRC files are been kept there. Every time we have to select that folder manually. This figure showed the DRC setup window.

For DRC setup, click on Inputs tab and make sure that

  • Run is DRC(Hierachical)
  • Export from Layout viewer is checked
  • Format is GDSII
  • To cell name is the name for which DRC is running

Now hit the Run DRC button on the left and the DRC run will start. It takes a while to check all the DRC rules. In final, a Calibre RVE windows will show where the errors are and you can click on the errors to locate the errors and revise them.

For LVS setup, we also have to click IBM_PDK>checking>calibre>LVS to open it. Then follow the previous setup for the environment setup. Then the window of LVS setup will open. We also have to set the LVS Run Directory. I created a new one so that all the LVS files are been kept there. But every time we have to select manually.

Click the input tab and make sure that

  • Hierarchical and Layout vs Netlist boxes are checked
  • On the middle layout tab, make sure that the Format is GDSII and export from Layout viewer is checked
  • Top cell name is the name for which LVS is running
  • Layout Netlist can be schematic_name.sp

Click the middle Netlist tab

  • make sure Format is SPICE and Export from schematic viewer is checked
  • Top cell name is the new for which LVS is running

Click the left Outputs tab

  • I also checked Generate data for Calibre-xRC and set the SVDB directory as svdb_schematicname.

Now hit the Run LVS button and the LVS run will start(hit ok when it ask to Overwrite file)

If you see the smiling face in LVS Report File, that means LVS passed. And you will also get the LVS RVE window with a green smiling face. Otherwise, you have to use LVS RVE window to check the errors.

The steps for LVS setup are shown in Figure1, Figure2, Figure3.

8. PEX: parasitic extraction

For the parasitic extraction using calibre, click IBM_PDK>checking>calibre>PEX. Follow the previous environment setup and click OK. Then the PEX interactive window will open. The PEX rules file is automatically loaded. Create a new folder to keep all PEX files. For future use, you have to select manually every time.

Click Inputs tab and make sure the Layout tab as

  • Format GDSII and check the Export from Layout viewer
  • The Layout file is xxx.calibre.db

Click Netlist tab in inputs

  • Format is SPICE and also check the Export from schematic viewer
  • The spice Files is xx.src.net

Click Outputs tab

  • Extraction Mode: xRC
  • Extraction Type: Transistor Level, R+C, No Inductance
  • Format:CALIBREVIEW, Use names from: Schematic
  • Check ‘View netlist after PEX finishes’

In the Reports under Outputs

  • check ‘view after run’ for PEX Report

For PEX Options, I also set the Ground node name ‘gnd!’ for netlist.

I attached several figures for PEX setup(Figure1, Figure2, Figure3, Figure4,Figure5,Figure6,Figure7)

Click Run PEX button. If PEX runs successfully, without any error, then you will be able to view PEX report File.

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