Basic Understanding of ASIC EDA Tool: Cadence Virtuoso

At first, I want to list some big EDA companies:

  • Cadence Design System
  • Mentor Graphics
  • Synopsys
  • Silvaco International

Cadence Virtuoso is the EDA tool of Cadence Design System for designing analog, RF or mixed-signal circuits.

Virtuoso provides the Virtuoso Schematic Editor for building up the circuit schematic. And we can use the ‘spectre’, ‘hspice’, or other simulator to check the schematic function.

Virtuoso provides the Virtuoso Layout Suite for physical implementation.  For doing the Design-Rule-Check(DRC) and Layout-vs-Schematic (LVS), we can use two different tools in Cadence. One is from Cadence itself: Assura DRC and LVS. The other one is from Mentor Graphics: Calibre DRC and LVS. Both are helpful for our physical transistor design. What’s more, we need the parasitic extraction to do the post-simulation for checking the chip design. We can use the QRC and PEX from Calibre for RC extraction.

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